Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
H
10Gbps MIPI D-PHY Hard Core (2.5Gbps/lane x4 data lanes+ Clock lane)
F
MSPI Programming
T
MG100T is pin compatible with the GW1NR-MG100PT
GW1NR(Integrated RAM)
GW1NR Series Table
Device
GW1NR-1
GW1NR-2
GW1NR-4
GW1NR-9
LUT4
1,152
2304
4,608
8,640
Flip-Flop (FF)
864
2304
3,456
6,480
ShadowSRAM SSRAM(bits)
0
0
0
17,280
Block SRAM BSRAM(bits)
72K
72K
180K
468K
Number of BSRAM
4
4
10
26
User Flash (bits)
96K
96K
256K
608K
SDR SDRAM(bits)
–
–
64M
64M
Embedded PSRAM(bits)
–
32-64M
32-64M
64-128M
NOR FLASH (bits)
4M
4M
–
–
18 x 18 Multiplier
0
0
16
20
PLLs
1
1
2
2
I/O Bank Number
4
7
4
4
Max. User I/O
120
126
218
276
Core Voltage (LV)
1.2V
1.2V
1.2V
1.2V
Core Voltage (UV)
–
1.8V/2.5V/3.3V
2.5V/3.3V
–
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch(mm)
Size(mm)
GW1NR-1
GW1NR-2
GW1NR-4
GW1NR-9
Identifier
QN88
0.4
10 x 10
–
–
70(11)
70(19)
QN88P
0.4
10 x 10
–
–
70(11)
70(17)
P
MG49P
0.5
3.8 x 3.8
–
30(8)
–
–
P
MG49PG
0.5
3.8 x 3.8
–
30(8)
–
–
PG
MG49G
0.5
3.8 x 3.8
–
30(8)
–
–
G
MG81P
0.5
4.5 x 4.5
–
–
68(10)
–
P
MG100P
0.5
5 x 5
–
–
–
87(16)
P
MG100PF
0.5
5 x 5
–
–
–
87(16)
PF
MG100PA
0.5
5 x 5
–
–
–
87(17)
PA
MG100PT
0.5
5 x 5
–
–
–
87(17)
PT
MG100PS
0.5
5 x 5
–
–
–
87(17)
PS
LQ144P
0.5
20 x 20
–
–
–
120(20)
P
EQ144G
0.5
20 x 20
112
–
–
–
G
EQ100G
0.5
14 x 14
75
–
–
–
G
FN32G
0.4
4 x 4
26
–
–
–
G
QN32X
0.5
5 x 5
26
–
–
–
X
QN48X
0.5
7 x 7
41
–
–
–
X
Package and Memory Information
Package
Device
Memory
Capacity
GW1NR-9
Identifier
QN88
GW1NR-4
SDR SDRAM
64M
16 bits
GW1NR-9
SDR SDRAM
64M
16 bits
QN88P
GW1NR-4
PSRAM
32M
8 bits
P
GW1NR-9
PSRAM
64M
16 bits
P
MG81P
GW1NR-4
PSRAM
64M
16 bits
P
MG100P
GW1NR-9
PSRAM
128M
32 bits
P
MG100PF
GW1NR-9
PSRAM
128M
32 bits
PF
MG100PA
GW1NR-9
PSRAM
128M
32 bits
PA
MG100PT
GW1NR-9
PSRAM
64M
16 bits
PT
MG100PS
GW1NR-9
PSRAM
64M
16 bits
PS
LQ144P
GW1NR-9
PSRAM
64M
16 bits
P
FN32G
EQ100G
EQ144G
QN32G
QN48G
GW1NR-1
NOR FLASH
4M
1 bit
G
MG49P
GW1NR-2
PSRAM
64M
16 bits
P
MG49G
GW1NR-2
NOR FLASH
4M
1 bit
G
MG49PG
GW1NR-2
PSRAM
32M (PSRAM)
8 bits
PG
NOR FLASH
4M (NOR FLASH)
1 bit
PG
Package Identifier Definition Table
Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
P
PSRAM
PG
PSRAM, Alternative Pinout
G
Alternative Pinout
PF
PSRAM, MSPI Programming
PA
AP memory PSRAM
PT
Two PSRAM, compatible with GW1NR-LV9MG100P
PS
Second PSRAM, compatible with GW1NR-LV9MG100PF
TheGW1NR embedded pSRAM memory products allow for more efficiency with on onboard memory and high-speed data rates. It has been optimized with Low Power, Small Size, and Thinnest Package in mind.
Features:
Embedded 64 Mb pSRAM
Supports 16-bit wide data, up to 166MHz clock rate/332Mbps data speeds
Small package sizes
Low power consumption
Dual Boot FPGA
Remote upgradeable bitstream
GW1NS(ARM Cortex-M3)
GW1NS Series Table
Parameter
GW1NS-4
GW1NS-4C
LUT4
4,608
4,608
FF
3,456
3,456
B-SRAM bits
180K
180K
B-SRAM quantity
10
10
18 x 18 Multiplier
16
16
S-SRAM bits
–
–
User Flash bits
256K
256K
PLLs
2
2
OSC
1,+/-5% accuracy
1,+/-5% accuracy
Hard Core Processor
–
Cortex-M3
I/O Banks
4
4
Max. User I/O
106
106
Core Voltage
1.2V
1.2V
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch(mm)
Size(mm)
GW1NS-4
GW1NS-4C
CS49
0.4
2.9 x 2.9
42(8)
42(8)
MG64
0.5
4.2 x 4.2
57(8)
57(8)
QN48
0.4
6 x 6
38(4)
38(4)
The GW1NS FPGA SoC device inherits the innovation of LittleBee™ family with embedded ARM Cortex-M3 hardcore processor, user flash, SRAM read/write controller providing customers all-in-one embedded solution with programable logic features in one chip. With Gowin integrated development environment, engineers can develop their hardware and software in a single platform, which is another innovation of FPGA design platform and reduces engineering design cycle.
Embedded 32-bit RISC Microprocessor
Arm Cortex-M3 (80 MHz)
32KB User Flash
Flash Configuration
Supports 2 image files
Supports Dual Boot
Online Upgradeable
Remote Upgrade
Integrated Development Flow for both M3 Core and FPGA Programming
Both the Cortex M3 IDE and GOWIN FPGA programming toolchain are integrated as one
Fixed MIPI D-PHY I/O
I/O’s are fixed to accept GOWIN control logic IP for a fully compliant CSI/DSI solution
GW1NSR Version includes:
32M-bits of embedded pSRAM memory
8-bit wide, 332Mbps data rates (166 MHz clock)
Real-Time Operating Systems Supported
uCOSIII
FreeRTOS
GW1NSE(R)(Security)
GW1NSE Secure FPGA Table
Parameter
GW1NS-4C
LUT4
4,608
FF
3,456
B-SRAM bits
180K
B-SRAM quantity
10
18 x 18 Multiplier
16
S-SRAM bits
–
User Flash bits
256K
PLLs
2
OSC
1,+/-5% accuracy
Hard Core Processor
Cortex-M3
I/O Banks
3
Max. User I/O
106
Core Voltage
1.2V
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch(mm)
Size(mm)
GW1NSE-4C
GW1NSER-4C
Identifier
QN48
0.4
6 x 6
–
–
LQ144
0.5
20 x 20
–
–
QN48P
0.4
6 x 6
–
38(4)
P
QN48G
0.4
6 x 6
–
38(4)
G
Package Identifier Definition Table
Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
P
PSRAM
G
Alternative Pinout
GW1NSE SecureFPGA products provide a Root of Trust based on SRAM PUF technology. Each device is factory provisioned with a unique key pair that is never exposed outside of the device. This widely applicable feature can be used for a variety of consumer and industrial IoT, edge and server management applications.
GW1NRF(Bluetooth LE)
GW1NRF Series Table
Device
GW1NRF-LV4B
LUT4
4,606
Flip-Flop (FF)
3,456
Shadow SRAM SSRAM (bits)
0
Block SRAM BSRAM (bits)
180K
Number of BSRAM
10
User Flash (bits)
256K
18 x 18 Multiplier
16
PLLs
2
I/O Bank Number
4
Max. User I/O
25
FPGA Core Voltage (LV)
1.2V
FPGA Core Voltage (UV)
1.8V/2.5V/3.3V
Bluetooth 5.0 LE RF
Yes
32-bit ARC Processor
Yes
Processor ROM (Bytes)
136K
Processor OTP (Bytes)
128K
Processor IRAM/DRAM (Bytes)
48K/28K
Security Core
Yes
Power Management Unit
Yes
DCDC Step Up/Down Regulator
Yes
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch (mm)
Size (mm)
GW1NRF-LV4B
QN48
0.4
6 x 6
25(4)
The GW1NRF Bluetooth FPGA product features FPGA fabric, a power optimized 32-bit microprocessor, a power management unit capable of power as low as 5nA and a Bluetooth 5.0 Low Energy radio. This extends the capabilities of Bluetooth devices by adding the flexible IO and heterogenous computing capabilities of the FPGA.
The GW1NRF BLE Module contains the GW1NRF-4 µSoC FPGA, radio antenna and appropriate passives.
Features
Integrated Bluetooth 5.0 Low Energy Radio
4k LUT FPGA
32-bit Power Optimized ARC Processor
– 136kB ROM
– 128kB OTP for power efficiency
– 48kB IRAM and 28kB DRAM
Power Management Unit
– 5nA Chip Disable1
– < 1uA Sleep and Deep Disable1
– < 5mA Processor + FPGA Active
Built-in DCDC Step Up/Down Regulator for Battery Operation
Hardened Security
– TRNG
– AES-128 Encryption Engine
ECC-P256 Key Generator
Module – International RF certifications available
Note!
[1]Does not include any leakage from external regulators when placed in standby
GW1NZ(Ultra Low Power)
GW1NZ Series Table
Device
GW1NZ-1
LUT4
1,152
Register
864
Shadow SRAM (bits)
4K
Block SRAM (bits)
72K
PLLs
1
User Flash (bits)
64K
Max. I/O
48
Core Voltage (LV)
1.2V
Core Voltage (ZV)
0.9V
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch (mm)
Size (mm)
GW1NZ-1
Identifier
QFN32
0.4
4 x 4
25
QFN32F
0.4
4 x 4
25
F
CS16
0.4
1.8 x 1.8
11
QFN48
0.4
6 x 6
40
Package Identifier Definition Table
Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
F
MSPI Programming
Note!
In this manual, abbreviations are employed to refer to the package types.
JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one.
GW1N-A(Automotive)
Product Resources
Device
GW1NZ-1
GW1N-2
GW1N-4
LUT4
1,152
2,304
4,604
Flip-Flop (FF)
864
2,304
3,456
Shadow SRAM Capacity (bits)
4K
0
0
Block SRAM Capacity (bits)
72K
72K
180K
Number of BSRAM
–
4
10
User Flash (bits)
64K
96K
256K
18 x 18 Multiplier
–
0
16
PLLs
1
1
2
Total Number of I/O banks
–
7
4
Max. I/O
48
126
218
Core Voltage (LV)
1.2V
1.2V
1.2V
Core Voltage (UV)
–
–
–
Core Voltage (ZV)
–
–
–
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch(mm)
Size(mm)
GW1NZ-1
GW1N-2
GW1N-4
Identifier
QN88
0.4
10 x 10
–
–
70(11)
QN88
0.4
10 x 10
–
58(17)
–
H
QN48
0.4
6 x 6
39
–
–
Note!
JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O is increased by one. See UG103, GW1N series of FPGA Products Package and Pinout for further
Package Identifier Definition Table
Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
H
10Gbps MIPI D-PHY Hard Core (2.5Gbps/lane x4 data lanes+ Clock lane)
Package Options, Available User I/O, (and LVDS Pairs):
Package
Pitch (mm)
Size(mm)
E-pad size (mm)
GW2A-18
GW2A-55
Identifier
QN88
0.4
10 x 10
6.74 x 6.74
66(22)
–
LQ144
0.5
20 x 20
–
119(34)
–
EQ144
0.5
20 x 20
9.74 x 9.74
119(34)
–
MG196
0.5
8 x 8
–
114(39)
–
PG256
1.0
17 x 17
–
207(73)
–
PG256S
1.0
17 x 17
–
192(72)
–
S
PG256SF
1.0
17 x 17
–
192(71)
–
SF
PG256C
1.0
17 x 17
–
190(64)
–
C
PG256CF
1.0
17 x 17
–
190(65)
–
CF
PG256E
1.0
17 x 17
–
162(29)
–
E
PG484
1.0
23 x 23
–
319(78)
319(76)
PG1156
1.0
35 x 35
–
–
607(97)
UG324
0.8
15 x 15
–
239(90)
240(86)
UG324F
0.8
15 x 15
–
–
240(86)
F
UG324D
0.8
15 x 15
–
–
240(71)
D
UG484
0.8
19 x 19
–
379(94)
–
UG484S
0.8
19 x 19
–
–
344(91)
UG676
0.8
21 x 21
–
–
525(97)
Package Identifier Definition Table
Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
F
Complementary device with the same pinout as S identifier; used as a secondary device for use cases requiring daisy chain SPI programming
D
UG324D offers an alternative pinout supporting two DDR3 interfaces instead of one DDR3 interface on UG324. Using all A side IOs in the IO pair and DDR3 utilizes an 8:1 gear ratio. Allowing it to run up to 800Mb/s across all temperatures and voltages compared to other IOs using both A and B at a 4:1 ratio.
GW2AN(Integrated Flash)
GW2AN Family Table
Device
GW2AN-9X
GW2AN-18X
GW2AN-55
LUT4
10368
20,736
54,720
Flip-Flop (FF)
10368
15,552
41,040
SSRAM(bits)
41472
41,472
109,440
BSRAM(bits)
540K
540K
2,520K
BSRAM quantity
30
30
140
NOR Flash
16M bit
16M bit
32M
PLLs
2
2
6
Global Clock
8
8
–
High Speed Clock
8
8
–
LVDS (Mb/s)
1250
1250
–
MIPI (Mb/s)
1200
1200
–
Total number of I/O
banks
9
9
8
Max. I/O
384
384
608
Core voltage (LV)
1.0V
1.0V
1.0V
Core voltage (EV)
1.2V
1.2V
–
Core voltage (UV)
2.5V/3.3V
2.5V/3.3V
–
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch (mm)
Size(mm)
GW2AN-9X
GW2AN-18X
GW2AN-55
Identifier
UG484
0.8
19 x 19
383(96)
383(96)
–
X
UG400
0.8
17 x 17
335(95)
335(95)
–
X
UG256
0.8
14 x 14
207(86)
207(86)
–
X
PG256
1.0
17 x 17
207(86)
207(86)
–
X
UG332
0.8
17 x 17
–
279(82)
–
X
UG324
0.8
15 x 15
279(74)
279(74)
–
UG676
0.8
21x 21
–
–
525（97）
Note!
JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The Max. I/O noted in this table is referred to when the four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O. For further detailed information, pelase refer toUG973, GW2ANseries of FPGA Products Package and Pinout .
GW2AR(Integrated RAM)
GW2AR Family Table
Device
GW2AR-18
LUT4
20,736
Flip-Flop (FF)
15,552
Shadow SRAM S-SRAM(bits)
41,472
Block SRAM B-SRAM(bits)
828K
Number of B-SRAM
46
PSRAM (bits)
64M
SDR/DDR SDRAM (bits)
64M / 128M
18 x 18 Multiplier
48
PLLs
4
I/O Bank Number
8
Max. User I/O
384
Core voltage
1.0V
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Pitch (mm)
Size(mm)
E-PAD Size (mm)
GW2AR-18
Identifier
LQ144
0.5
20 x 20
–
120(35)
EQ144
0.5
20 x 20
9.74 x 9.74
120(35)
EQ144P
0.5
20 x 20
9.74 x 9.74
120(35)
P
EQ144PF
0.5
20 x 20
9.74 x 9.74
120(35)
PF
QN88
0.4
10 x 10
6.74 x 6.74
66(22)
QN88P
0.4
10 x 10
6.74 x 6.74
66(22)
P
QN88PF
0.4
10 x 10
6.74 x 6.74
66(22)
PF
LQ176
0.4
20 x 20
–
140(45)
EQ176
0.4
20 x 20
6 x 6
140(45)
PG256S
1.0
17 x 17
–
192(62)
S
Package Identifier Definition Table
Feature identifier table denotes additional device capabilities outside of the traditional FPGA options
P
PSRAM
PF
PSRAM, MSPI Programming
GW2ANR(Flash+RAM)
GW2ANR Family Table
Device
GW2ANR-18
LUT4
20,736
Flip-Flop (FF)
15,552
Shadow SRAM S-SRAM(bits)
41,472
Block SRAM B-SRAM(bits)
828K
Number of B-SRAM
46
NOR FLASH (bits)
32M
SDR SDRAM (bits)
64M
18 x 18 Multiplier
48
PLLs
4
I/O Bank Number
8
Max. User I/O on die
384
Core voltage
1.0V
Package Options, Availible User I/O, (and LVDS Pairs):
Package
Device
Memory
Bit Width
Capacity
PLL
QN88
GW2ANR-18
SDR SDRAM
32 bits
64M bits
PLLL1/PLLR1
NOR FLASH
1 bit
32M bits
GW2ANR-18
Package
Pitch(mm)
Size(mm)
E-PAD Size(mm)
GW2AR-18
QN88
0.4
10 x 10
6.74 x 6.74
66(22)
GW2A-A(Automotive)
GW2A-A Family Table
Parameter
GW2A-LV18 A6
LUT4
20,736
Flip-Flop(FF)
15,552
Block SRAM (bits)
828K
User Flash(bits)
–
18 x 18 Multiplier
48
PLLs
4
I/O banks
8
Core Voltage (LV)
1.0V
Packages
QFN88
BG256
# User IO
66(22)
207(73)
GOWIN Semiconductor has been manufacturing automotive grade FPGA since early 2018. Providing fully certified AEC-Q100 Level-2 non-volatile Flash-based and SRAM FPGA devices that support a wide range of interface standards including MIPI-DPHY and LVDS.
GOWIN AEC-Q100 automotive qualified devices are ideally suited for interfacing and bridging camera sensors and displays for ADAS, 360o surround view, infotainment systems and LCD dashboard applications as well as system control, monitoring and management applications.
Over 10 complete solutions have been developed, many of which have passed vehicle installation tests in a number of leading top automotive companies.
2014年に設立され、主要なR＆Dを中国本社に置くGowinセミコンダクターは、プログラマブル・ソリューションで世界的に顧客のイノベーションを加速するビジョンを持っています。
